The present invention relates to methods for fabricating semiconductor devices, and particularly relates to a semiconductor device including a gate insulating film made of a dielectric material having a high dielectric constant (hereinafter, referred to as a high-κ material) and a method for fabricating the device.
With recent increase in the integration degree and speed of semiconductor integrated circuit devices and expansion of the functionality thereof, the size of metal-oxide-semiconductor field effect transistors (MOSFETs) has been reduced. As the thickness of a gate insulating film decreases in accordance with this size reduction, the problem of increased gate leakage current caused by tunnel current comes to the surface. To solve this problem, there has been developed a technique with which a high-κ material of metal oxide such as hafnium oxide (HfO2) or zirconium oxide (ZrO2) is used for a gate insulating film so that the equivalent oxide thickness EOT is reduced with a physical thickness increased. The equivalent oxide thickness EOT is herein a thickness calculated from the thickness of a film made of a dielectric having a relative dielectric constant different from that of silicon oxide (SiO2) in terms of the relative dielectric constant of silicon oxide.
In the initial stage of development, the use of a gate insulating film made of metal oxide such as HfO2 or ZrO2 causes a problem in which an interface layer is formed between a silicon substrate and the gate insulating film. This interface layer has a low dielectric constant, so that the effective relative dielectric constant of the gate insulating film decreases, i.e., the equivalent oxide thickness EOT increases. Therefore, it was necessary to suppress formation of such an interface layer as much as possible. However, once the formation of an interface layer was successfully suppressed so that a high effective relative dielectric constant of the gate insulating film is maintained, i.e., the equivalent oxide thickness EOT is reduced afterward, there arises another problem in which carrier mobility deteriorates as compared to the case of a silicon oxide film and, consequently, desired operating current cannot be obtained. It has been considered that a cause of this problem is that (1) fixed charge included in a high-κ material electrically interferes with carriers in channel to cause the carrier mobility to deteriorate or (2) carriers in channel are scattered by a lattice in the high-κ material to cause the carrier mobility to deteriorate, for example. In Non-patent literature 1 (M. Hiratani, S. Saito, Y. Shimamoto, and K. Torii, “Effective Electron Mobility Reduced by Remote Charge Scattering in High-κ Gate Stacks”, Jpn. J. Appl. Phys., Part 1 84, (2002), pp. 4512-4522), for example, a relationship between the mobility and the thickness of a silicon oxide film formed at the interface between a silicon substrate and a gate insulating film. According to this relationship, to avoid deterioration of the carrier mobility, channel (a substrate) and a high-κ material (a gate insulating film) are preferably separated from each other or a silicate structure in which a metal concentration in the entire high-κ material is reduced is preferably used. However, since the interface layer made of, for example, a silicon oxide film has a low relative dielectric constant, the effective relative dielectric constant of the gate insulating film extremely decreases, i.e., the equivalent oxide thickness EOT increases, in a case where the thickness of the interface layer is relatively large or in the case of a silicate structure in which the metal concentration is relatively low. Accordingly, each of a structure including an interface layer and a structure having a reduced metal concentration has a trade-off relationship with the case of not adopting these structures.
In addition, the use of a high-κ material for a gate insulating film causes another problem. That is, the absolute value of the threshold voltage Vt during transistor operation increases due to reaction at the upper interface of the gate insulating film, i.e., reaction between materials for the gate electrode and the gate insulating film. Though a cause of this problem is unclear, it is reported that exposure to a high-temperature process in a transistor process such as activation performed on ions implanted in source/drain regions causes a gate-electrode material and an gate-insulating-film material to react with each other, so that an effective work function of the gate-electrode material varies. This phenomenon is called Fermi-level pinning. For example, in Non-patent literature 2 (C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, “Fermi level pinning at the polySi/metal oxide interface”, Proceedings of the 2003 Symposium on VLSI Technology, (2003), pp. 9-10), it is reported that in a case where a gate-electrode material is polysilicon, the effective work function of the material is fixed at a position near the midgap (i.e., the intermediate value of band gap energy) of silicon and toward the conduction band, i.e., near the work function of n-type doped polysilicon, irrespective of the type of the dopant for polysilicon and, as a result, the absolute value of the threshold voltage Vt of a pMOSFET using a p-type doped polysilicon electrode is considerably large. In addition, regarding this Fermi-level pinning, inversion capacitance of the pMOSFET greatly decreases, which becomes a major obstacle to the use of a high-κ material for a gate insulating film and polysilicon for a gate electrode.
As a means for avoiding Fermi-level pinning occurring when polysilicon is used for a gate electrode, a metal-gate transistor structure using a metal having an appropriate work function and a so-called full-silicidation (FUSI) gate transistor structure in which not only an upper portion but also the entire portion of a polysilicon gate electrode is silicided has been proposed. However, for the metal-gate transistor structure, even when a metal having a high melting point is used as a gate-electrode material, a high-temperature process such as activation on source/drain regions is performed, so that Fermi-level pinning occurs and a desired work function is not obtained. In a case where a semiconductor device has a complementary MOS structure (i.e., a CMOS structure) including a pMOSFET and an nMOSFET, a dual-metal structure including metals having work functions appropriate for the respective pMOSFET and nMOSFET is needed. However, this structure has the problem of uneasiness of processes such as gate etching.
For the FUSI gate transistor structure, a high-temperature process such as activation on source/drain regions is performed and then a polysilicon gate electrode is subjected to full-silicidation. In other words, polysilicon forming the gate electrode is replaced with metal silicide. In this case, when a CMOS structure is adopted, metal silicides having work functions appropriate for a pMOSFET and an nMOSFET are needed for the respective gate electrodes. In Non-patent literature 3 (K. Takahashi, K. Manabe, T. Ikarashi, N. Ikarashi, T. Hase, T. Yoshihara, H. Watanabe, T. Tatsumi and Y. Mochizuki, “Dual Workfunction Ni-Silicide/HfSiON Gate Stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45 nm-node LSTP and LOP Devices”, IEDM Tech. Dig., (2004), pp. 91-94), the possibility of controlling the work function by varying the proportions of metal nickel and silicon in metal silicide is proposed. However, Fermi-level pinning still occurs in this case, and a desired work function is not obtained. Moreover, no specific process flows for implementing a CMOS structure are clarified. In Non-patent literature 4 (C. S. Park, B. J. Cho, L. J. Tang, and D. L. Kwong, “Substituted Aluminum Metal Gate on High-K Dielectric for Low Work-Function and Fermi-Level Pinning Free”, IEDM Tech. Dig., (2004), pp. 299-302), insufficient uniformity and poor yield of a FUSI gate process itself are reported.